MPC8540 datasheet(559/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-55

Note that during normal operation (read/write), a full 32-bit address that includes row and column

is generated on LAD[0:31]. However, address/data signal multiplexing implies that the address

must be latched by an external latch that is controlled by LALE. All SDRAM device address

signals need to be connected to the latched address bits and burst address bits (LA[27:31]) of the

LBC, with the exception of A10, which has a dedicated connection on LSDA10. LSDA10 is

driven with the appropriate row address bit for SDRAM commands that require A10 to be an

address.

13.4.3.7

SDRAM Device-Specific Parameters

The software is responsible for setting correct values for device-specific parameters that can be

extracted from the device’s data sheet. The values are stored in the ORn and LSDMR registers.

These parameters include the following:

•

Precharge to activate interval (LSDMR[PRETOACT])

•

Activate to read/write interval (LSDMR[ACTTORW])

•

CAS latency, column address to first data out (LSDMR[CL] and LCRR[ECL])

•

Write recovery, last data in to precharge (LSDMR[WRC])

•

Refresh recovery interval (LSDMR[RFRC])

•

External buffers on the control lines present (LSDMR[BUFCMD] and

LCRR[BUFCMDC])

In addition, the LBC hardware ensures a default activate to precharge interval of 10 bus cycles.

The following sections describe SDRAM parameters programmed in LSDMR.

13.4.3.7.1 Precharge-to-Activate Interval

The precharge-to-activate interval parameter, controlled by LSDMR[PRETOACT]. defines the

earliest timing for an ACTIVATE or REFRESH command after a PRECHARGE command to the

same SDRAM bank.

Figure 13-35. PRETOACT = 2 (2 Clock Cycles)

1111

0000

1111

ZZZZZZZZ RAS ADD

XXXXX

CAS ADD

ZZZZZZZZ

LCLK

LALE

LCSn

LSDRAS

LSDCAS

LSDWE

LSDDQM[0:3]

LAD[0:31]

PRETOACT = 2

PRECHARGE

Command

Bank A

ACTIVATE

Command

Bank A

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