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MPC8540 Datasheet(PDF) 562 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 562 Page - Freescale Semiconductor, Inc |
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562 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 13-58 Freescale Semiconductor Local Bus Controller Figure 13-40. BUFCMD = 1, LCRR[BUFCMDC] = 2 13.4.3.8 SDRAM Interface Timing The following figures show SDRAM timing for various types of accesses. Figure 13-41. SDRAM Single-Beat Read, Page Closed, CL = 3 Figure 13-42. SDRAM Single-Beat Read, Page Hit, CL = 3 Figure 13-43. SDRAM Two-Beat Burst Read, Page Closed, CL = 3 1111 0000 1111 ZZZZZZ RAS ADD XXXXXXXX CAS ADD D3 ZZZZZZZZ LCLK LALE LCSn LSDRAS LSDCAS LSDWE LSDDQM LAD D0 D1 D2 XXXX Command setup cycle Command setup cycle 1111 0000 1111 ZZZZZZZZ ZZZZZZZZ ZZZZZZZZ D0 ZZZZZZZZ LCLK LALE LCSn LSDRAS LSDCAS LSDWE LSDDQM[0:3] LAD[0:31] COL ADD ROW ADD TA 1111 0000 1111 ZZZZZZZZ COL ADD ZZZZZZZZ LCLK LALE LCSn LSDRAS LSDCAS LSDWE LSDDQM[0:3] LAD[0:31] TA D0 1111 0000 1111 ZZZZZZZZ ZZZZZZZZ ZZZZZZZZ D0 ZZZZZZZZ LCLK LALE LCSn LSDRAS LSDCAS LSDWE LSDDQM[0:3] LAD[0:31] COL ADD ROW ADD TA D1 |
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