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MPC8540 Datasheet(PDF) 566 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 566 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
13-62
Freescale Semiconductor
Local Bus Controller
Figure 13-51. SDRAM Bank-Staggered Auto-Refresh Timing
13.4.4 User-Programmable Machines (UPMs)
UPMs are flexible interfaces that connect to a wide range of memory devices. At the heart of each
UPM is an internal RAM array that specifies the logical value driven on the external memory
control signals1 (LCSn, LBS[0:3] and LGPL[0:5]) for a given clock cycle. Each word in the RAM
array provides bits that allow a memory access to be controlled with a resolution of up to one
quarter of the external bus clock period on the byte-select and chip-select lines. Figure 13-52
shows the basic operation of each UPM.
Figure 13-52. User-Programmable Machine Functional Block Diagram
1.If the LGPL4/LGTA/LUPWAIT/LPBSE signal is used as both an input and an output, a weak pullup is required.
Refer to the hardware specification for details regarding termination options.
1111
0000
1111
Z
ROW ADD
X
COL ADD
D0
Z
LCLK
LALE
LCS1
LCS2
LCS3
LCS4
LSDRAS
LSDCAS
LSDWE
LSDDQM[0:3]
LAD[0:31]
TA
Auto
Ref
Auto
Ref
Auto
Ref
Auto
Ref
Activate
LSDMR[RFCR]
Run Command
UPM Refresh
Timer Request
Array
Index
Generator
Internal / External
Memory Access Request
Exception Request
Index
Signals
Timing
Generator
Internal
Signals
Latch
Wait
Request
Logic
RAM Array
LUPWAIT
WAEN Bit
Internal Controls
LGPLn
Increment
Index
(LAST = 0)
Hold
(issued in software)
LBSn
LCSn



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