MPC8540 datasheet(564/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-60

Freescale Semiconductor

Local Bus Controller

Figure 13-48. SDRAM Write-after-Write Pipelined, Page Hit

Figure 13-49. SDRAM Read-after-Write Pipelined, Page Hit

13.4.3.9

SDRAM Read/Write Transactions

The SDRAM interface supports read and write transactions of between 1 and 8 data beats for

transaction sizes ranging from 1 to 32 bytes. A full burst is performed for each transaction, with

the burst length dependent on the port size. A maximum burst of 8 beats is used for an 8-bit or

32-bit port size, while a maximum burst of 4 beats is used for a 16-bit port size, as programmed in

LSDMR[BL]. For reads that require less than the full burst length, extraneous data in the burst is

ignored and suppressed by the assertion of LSDDQM[0:3]. For writes that require less than the

full burst length, the non-targeted addresses are protected by driving corresponding LSDDQM bits

high (inactive) on the irrelevant cycles of the burst. However, system performance is not

compromised because, if a new transaction is pending, the SDRAM controller begins executing it

immediately, effectively terminating the burst early.

13.4.3.10 SDRAM MODE-SET Command Timing

The LBC transfers mode register data (CAS latency and burst length) stored in the LSDMR

In this case, the latched address carries the mode bits for the command.

1111

0000

1111

0000

COL ADD 1

COL ADD 2

LCLK

LALE

LCSn

LSDRAS

LSDCAS

LSDWE

LSDDQM[0:3]

LAD[0:31]

1111

0000

1111

0000

1111

COL ADD 1

COL ADD 2

LCLK

LALE

LCSn

LSDRAS

LSDCAS

LSDWE

LSDDQM[0:3]

LAD[0:31]

MPC8540 Datasheet(PDF) 564 Page - Freescale Semiconductor, Inc

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