MPC8540 datasheet(560/1302 Pages) FREESCALE

560 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-56

Freescale Semiconductor

Local Bus Controller

13.4.3.7.2 Activate-to-Read/Write Interval

This parameter, controlled by LSDMR[ACTTORW], defines the earliest timing for a

READ/WRITE command after an ACTIVATE command to the same SDRAM bank.

Figure 13-36. ACTTORW = 2 (2 Clock Cycles)

13.4.3.7.3 Column Address to First Data Out—CAS Latency

This parameter, controlled by LSDMR[CL] for latency of 1, 2, or 3 and by LCRR[ECL] for

latency of more than 3, defines the timing for first read data after a column address is sampled by

the SDRAM.

Figure 13-37. CL = 2 (2 Clock Cycles)

13.4.3.7.4 Last Data In to Precharge—Write Recovery

This parameter, controlled by LSDMR[WRC], defines the earliest timing for a PRECHARGE

command after the last data was written to the SDRAM.

1111

0000

1111

ZZZZZZZZ

RAS ADD

XXXX

CAS ADD

ZZZZZZZZ

LCLK

LALE

LCSn

LSDRAS

LSDCAS

LSDWE

LSDDQM[0:3]

LAD[0:31]

ACTTORW = 2

ACTIVATE

Command

WRITE

Command

1111

0000

1111

ZZZZZZZZ

RAS ADD

ZZZZZZZZ

CAS_ADD

LCLK

LALE

LCSn

LSDRAS

LSDCAS

LSDWE

LSDDQM[0:3]

LAD[0:31]

XXXX

CL = 2

READ

Command

First Data Out

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