MPC8540 datasheet(557/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-53

data inputs on the rising edge of the bus clock. Data at the output of the SDRAM device is sampled

on the rising edge of the bus clock.

The following SDRAM interface commands are provided by setting LSDMR[OP] to a non-zero

value (LSDMR[OP] = 000 sets normal read/write operation):

13.4.3.4

Page Hit Checking

The SDRAM machine supports page-mode operation. Each time a page is activated on the

SDRAM device, the SDRAM machine stores its address in a page register. The page information,

which the user writes to the ORn register, is used along with the bank size to compare page bits of

Table 13-28. SDRAM Interface Commands

Command

(LSDMR[OP])

Description

ACTIVATE

(110)

Latches the row address and initiates a memory read of that row. Row data is latched in SDRAM

sense amplifiers and must be restored with a PRECHARGE command before another ACTIVATE

is issued.

MODE-SET

(011)

Allows setting of SDRAM options—CAS latency and burst length. CAS latency depends on the

SDRAM device used. Although some SDRAMs provide burst lengths of 1, 2, 4, 8, or a page, the

local bus memory controller supports only 8-beat bursts for 8-bit and 32-bit port size, or 4-beat

bursts for 16-bit port size. The LBC does not support burst lengths of 1, 2 and a page for SDRAMs.

The mode register data (CAS latency and burst length) is programmed into the LSDMR register by

initialization software after reset. After the LSDMR is set, the LBC transfers the information to the

SDRAM device by issuing a MODE-SET command.

PRECHARGE

(100: single bank)

(101: all-banks)

Restores data from the sense amplifiers to the appropriate row in the SDRAM device array. Also

initializes the sense amplifiers to prepare for activating another row in the SDRAM device. Note that

the LBC uses LSDA10 to distinguish between PRECHARGE-ALL-BANKS (LSDA10 is high) and

PRECHARGE-SINGLE-BANK (LSDA10 is low). The SDRAMs must be compatible with this format.

READ

(111)

Latches the column address and transfers data from the selected sense amplifier on the SDRAM

device, to the output buffer as determined by the column address. During each successive clock,

additional data is driven without additional read commands. At the end of the burst, the page

remains open. Burst length is the one set for this bank. Read data is discarded by the LBC.

WRITE

(111)

Latches the column address and transfers data from the data signals to the selected sense amplifier

on the SDRAM device, as determined by the column address. During each successive clock,

additional data is transferred to the sense amplifiers from the data signals without additional write

commands. At the end of the burst, the page remains open. Burst length is the one set for this bank.

LSDDQM[0:3] are inactive and write data is undefined.

AUTO-REFRESH

(001)

Causes a row to be read in all memory banks (JEDEC SDRAM) as determined by the refresh row

address counter (similar to CBR). The refresh row address counter is internal to the SDRAM device.

After being read, a row is automatically rewritten into the memory array. All banks must be in a

precharged state before executing refresh.

SELF-REFRESH

(010)

Allows data to be retained in the SDRAM device, even when the rest of the LBC is in a power saving

mode with clocks turned off. When placed in this mode, the SDRAM device is capable of issuing its

own refresh commands, without external clocking from the LBC and the LCKE pin from the LBC is

negated. This command can be issued at any time. Normal operation can be resumed only by

setting LSDMR[OP] = 000, and waiting a minimum of 200 bus cycles before issuing reads or writes

to the LBC.

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