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MPC8540 Datasheet(PDF) 553 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 553 Page - Freescale Semiconductor, Inc |
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553 / 1302 page ![]() Functional Description MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 13-49 Figure 13-30. GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) Figure 13-31. GPCM Read Followed by Write (TRLX = 0, EHTR = 1, 1-Cycle Extended Hold Time on Reads) 13.4.2.3 External Access Termination (LGTA) External access termination is supported by the GPCM using the asynchronous LGTA input signal, which is synchronized and sampled internally by the local bus. If, during assertion of LCSn, LCLK LAD LALE LCSn LBCTL Address 1 A Latched Address 1 TA LOE Read Data 1 Address 2 Data 2 Latched Address 2 LCSy Bus turnaround LCLK LAD LALE LCSn LBCTL Rd. Address A Latched Read Address TA LOE Wr. Address Wr. Address LCSy Extended hold Bus turnaround Wr. Data Read Data |
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