MPC8540 datasheet(549/1302 Pages) FREESCALE

549 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-45

Figure 13-25. GPCM Basic Write Timing (XACS = 0, ACS = 00, CSNT = 1, SCY = 1,

TRLX = 0, CLKDIV = 4 or 8)

As Figure 13-25 shows, the timing for LCSn is the same as for the latched address. The strobes for

the transaction are supplied by LOE or LWEn, depending on the transaction direction—read or

write (write case shown in Figure 13-25). ORn[CSNT] controls the timing for the appropriate

strobe negation in write cycles. When this attribute is asserted, the strobe is negated one quarter of

a clock before the normal case provided that LCRR[CLKDIV] = 4 or 8. For example, when

ACS = 00 and CSNT = 1, LWEn is negated one quarter of a clock earlier, as shown in

Figure 13-25. If LCRR[CLKDIV] = 2, LWEn is negated either coincident with LCSn or one cycle

earlier.

13.4.2.2.3 Relaxed Timing

ORx[TRLX] is provided for memory systems that require more relaxed timing between signals.

Setting TRLX = 1 has the following effect on timing:

•

An additional bus cycle is added between the address and control signals (but only if

ACS

≠ 00).

•

The number of wait states specified by SCY is doubled, providing up to 30 wait states.

•

The extended hold time on read accesses (EHTR) is extended further.

•LCSn signals are negated 1 cycle earlier during writes (but only if ACS

≠ 00).

•LWE[0:3] signals are negated 1 cycle earlier during writes.

LCLK

LAD

LALE

LCSn

LWEn

Address

Write Data

Latched Address

LOE

CSNT = 1

SCY = 1

MPC8540 Datasheet(PDF) 549 Page - Freescale Semiconductor, Inc