MPC8540 datasheet(548/1302 Pages) FREESCALE

548 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-44

Freescale Semiconductor

Local Bus Controller

13.4.2.2

Chip-Select Assertion Timing

The banks selected to work with the GPCM, support an option to drive the LCSn signal with

different timings (with respect to the external address/data bus). LCSn can be driven in any of the

following ways:

•

Simultaneous with the latched memory address. (This refers to the externally latched

address and not the address timing on LAD[0:31]. That is, chip select does not assert during

LALE).

•

One quarter of a clock cycle later (for LCRR[CLKDIV] = 4 or 8).

•

One half of a clock cycle later (for LCRR[CLKDIV] = 2, 4, or 8).

•

One clock cycle later (for LCRR[CLKDIV] = 4), when ORn[XACS] = 1.

•

Two clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when ORn[XACS] = 1.

•

Three clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when ORn[XACS] = 1 and

ORn[TRLX] = 1.

The timing diagram in Figure 13-24 shows two chip-select assertion timings for the case

LCRR[CLKDIV] = 4 or 8. If LCRR[CLKDIV] = 2, LCSn asserts identically for ORn[ACS] = 10

or 11.

13.4.2.2.1 Programmable Wait State Configuration

The GPCM supports internal generation of transfer acknowledge. It allows between zero and 30

wait states to be added to an access by programming ORn[SCY] and ORn[TRLX]. Internal

generation of transfer acknowledge is enabled if ORn[SETA] = 0. If LGTA is asserted externally

two bus clock cycles or more before the wait state counter has expired (to allow for

synchronization latency), the current memory cycle is terminated by LGTA; otherwise it is

terminated by the expiration of the wait state counter. Regardless of the setting of ORn[SETA],

wait states prolong the assertion duration of both LOE and LWEn in the same manner. When

TRLX = 1, the number of wait states inserted by the memory controller is doubled from

ORn[SCY] cycles to 2

× ORn[SCY] cycles, allowing a maximum of 30 wait states.

13.4.2.2.2 Chip-Select and Write Enable Negation Timing

Figure 13-23 shows a basic connection between the local bus and a static memory device. In this

case, LCSn is connected directly to CE of the memory device. The LWE[0:3] signals are

connected to the respective WE[3:0] signals on the memory device where each LWE[0:3] signal

corresponds to a different data byte.

MPC8540 Datasheet(PDF) 548 Page - Freescale Semiconductor, Inc

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