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MPC8540 Datasheet(PDF) 544 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 544 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
13-40
Freescale Semiconductor
Local Bus Controller
shows signal behavior and system response for a write access with LCRR[CLKDIV] = 4 or
LCRR[CLKDIV] = 8. Table 13-24 shows the signal behavior and system response for a read
access with LCRR[CLKDIV] = 4 or LCRR[CLKDIV] = 8. Table 13-25 and Table 13-26 show the
write and read signal behavior, respectively, when LCRR[CLKDIV] = 2.
Table 13-23. GPCM Write Control Signal Timing for LCRR[CLKDIV] = 4 or 8
Option Register Attributes
Signal Behavior (Bus Clock Cycles)
TRLX
XACS
ACS
CSNT
Address to
LCSn Asserted
LCSn Negated to
Address Change
LWE Negated to
Address/Data Invalid
Total Cycles1
1 Total cycles when LALE is asserted for one cycle only (ORn[EAD] = 0; ORn[EAD] = 1 and LCRR[EADC] = 01).
Asserting LALE for more than one cycle increases the total cycle count accordingly.
0
0
00
0
0
0
0
3+SCY
0
0
10
0
1/4
0
0
3+SCY
0011
0
1/2
0
0
3+SCY
0
1
00
0
0
0
0
3+SCY
0
1
10
0
1
0
0
3+SCY
0111
0
2
0
0
4+SCY
0
0
00
1
0
0
–1/4
3+SCY
0
0
10
1
1/4
–1/4
–1/4
3+SCY
0
0
11
1
1/2
–1/4
–1/4
3+SCY
0
1
00
1
0
0
–1/4
3+SCY
0
1
10
1
1
–1/4
–1/4
3+SCY
0
1
11
1
2
–1/4
–1/4
4+SCY
1
0
00
0
0
0
0
3+2*SCY
1
0
10
0
1+1/4
0
0
4+2*SCY
1011
0
1+1/2
0
0
4+2*SCY
1
1
00
0
0
0
0
3+2*SCY
1
1
10
0
2
0
0
4+2*SCY
1111
0
3
0
0
5+2*SCY
1
0
00
1
0
0
–1–1/4
4+2*SCY
1
0
10
1
1+1/4
–1–1/4
–1–1/4
5+2*SCY
1
0
11
1
1+1/2
–1–1/4
–1–1/4
5+2*SCY
1
1
00
1
0
0
–1–1/4
4+2*SCY
1
1
10
1
2
–1–1/4
–1–1/4
5+2*SCY
1
1
11
1
3
–1–1/4
–1–1/4
6+2*SCY



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