MPC8540 datasheet(541/1302 Pages) FREESCALE

541 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-37

Figure 13-22. Basic LBC Bus Cycle with LALE, TA, and LCSn

13.4.1.4

Data Buffer Control (LBCTL)

The memory controller provides a data buffer control signal for the local bus (LBCTL). This signal

is activated when a GPCM or UPM controlled bank is accessed. LBCTL can be disabled by setting

ORn[BCTLD]. Access to an SDRAM machine controlled bank does not activate the LBCTL

control. LBCTL can be further configured by LBCR[BCTLC] to act as an extra LWE or an extra

LOE signal when in GPCM mode.

If LBCTL is configured as a data buffer control (LBCR[BCTLC] = 00), the signal is asserted

(high) on the rising edge of the bus clock on the first cycle of the memory controller operation,

coincident with LALE. If the access is a write, LBCTL remains high for the whole duration.

However, if the access is a read, LBCTL is negated (low) with the negation of LALE so that the

memory device is able to drive the bus. If back-to-back read accesses are pending, LBCTL is

asserted (high) one bus clock cycle before the next transaction starts (that is, one bus clock cycle

before LALE) to allow a whole bus cycle for the bus to turn around before the next address is

driven.

If an external bus transceiver is used, LBCTL should be used to signify the write direction when

high. Note that the default (reset and bus idle) value of LBCTL is also high.

13.4.1.5

Atomic Operation

The LBC supports the following kinds of atomic bus operations (set by BRn[ATOM]):

•

Read-after-write atomic (RAWA). When a write access hits a memory bank in which

ATOM = 01, the LBC reserves the selected memory bank for the exclusive use of the

accessing master.

While the bank is reserved, no other device can be granted access to this bank. The

reservation is released when the master that created it accesses the same bank with a read

transaction. Additional write transactions prior to the releasing read do not change

reservation status, but are otherwise processed normally. If the master fails to release the

LAD

LALE

LCSn

Address

Data

LCLK

MPC8540 Datasheet(PDF) 541 Page - Freescale Semiconductor, Inc