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MPC8540 Datasheet(PDF) 543 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 543 Page - Freescale Semiconductor, Inc

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Functional Description
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
13-39
Also, the output enable signal (LOE) is provided to minimize external glue logic. On system reset,
a global (boot) chip-select is available that provides a boot ROM chip-select (LCS0) prior to the
system being fully configured.
Figure 13-23. Local Bus to GPCM Device Interface
Figure 13-24 shows LCS as defined by the setup time required between the address lines and CE.
The user can configure ORn[ACS] to specify LCS to meet this requirement.
Figure 13-24. GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0,
CLKDIV = 4,8)
13.4.2.1
Timing Configuration
If BRn[MSEL] selects the GPCM, the attributes for the memory cycle are taken from ORn. These
attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR, and SETA fields. Table 13-23
CE
OE
W[3:0]
Data[7:0]
Memory/Peripheral
LALE
LWE[0:3]
LOE
LCSn
LA[30:31]
LA[27:29]
LAD[12:26]
A[19:5]
A[4:2]
A[0:1]
LBC in GPCM
Mode
Latch
LAD[0:7]
LCLK
LAD
LALE
LCSn
LOE
Address
Read Data
A[19:5]
Latched Address
TA
ACS = 11
ACS = 10



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