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MPC8540 Datasheet(PDF) 547 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 547 Page - Freescale Semiconductor, Inc

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Functional Description
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
13-43
Table 13-26. GPCM Read Control Signal Timing for
LCRR[CLKDIV] = 2
Option Register Attributes
Signal Behavior (Bus Clock cycles)
TRLX EHTR XACS ACS Address to LCSn Asserted LCSn Negated to Address Change Total Cycles1
1 Total cycles when LALE is asserted for 1 cycle only (ORn[EAD]=0; ORn[EAD]=1 and LCRR[EADC]=01).
Asserting LALE for more than 1 cycle increases the total cycle count accordingly.
00
0
00
0
1
4+SCY
00
0
10
1/2
1
4+SCY
00
0
11
1/2
1
4+SCY
00
1
00
0
1
4+SCY
00
1
10
1
1
4+SCY
00
1
11
2
1
5+SCY
01
0
00
0
2
5+SCY
01
0
10
1/2
2
5+SCY
01
0
11
1/2
2
5+SCY
01
1
00
0
2
5+SCY
01
1
10
1
2
5+SCY
01
1
11
2
2
6+SCY
10
0
00
0
5
8+2*SCY
10
0
10
1+1/2
5
9+2*SCY
10
0
11
1+1/2
5
9+2*SCY
10
1
00
0
5
8+2*SCY
10
1
10
2
5
9+2*SCY
1
0
1
11
3
5
10+2*SCY
1
1
0
00
0
9
12+2*SCY
1
1
0
10
1+1/2
9
13+2*SCY
1
1
0
11
1+1/2
9
13+2*SCY
1
1
1
00
0
9
12+2*SCY
1
1
1
10
2
9
13+2*SCY
1
1
1
11
3
9
14+2*SCY



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