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MPC8540 Datasheet(PDF) 551 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 551 Page - Freescale Semiconductor, Inc |
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551 / 1302 page  Functional Description MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 13-47 Figure 13-26 and Figure 13-27 show relaxed timing read and write transactions. The effect of CLKDIV = 2 for these examples is only to delay the assertion of LCSn in the ACS = 10 case to the ACS = 11 case. The example in Figure 13-27 also shows address and data multiplexing on LAD[0:31] for a pair of writes issued consecutively. When TRLX and CSNT are set in a write access, the LWE[0:3] strobe signals are negated one clock earlier than in the normal case, as shown in Figure 12-28 and Figure 12-29. If ACS ≠ 00, LCSn is also negated one clock earlier. Figure 13-28. GPCM Relaxed Timing Write (XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1, CLKDIV = 4 or 8) LCLK LAD LALE LCSn LBCTL Address A Latched Address TA LWEn ACS = 10 Write Data LOE CSNT = 1 |
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