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MPC8540 Datasheet(PDF) 554 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 554 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
13-50
Freescale Semiconductor
Local Bus Controller
the sampled LGTA signal is asserted, it is converted to an internal generation of transfer
acknowledge, which terminates the current GPCM access (regardless of the setting of
ORn[SETA]). LGTA should be asserted for at least one bus cycle to be effective. Note that because
LGTA is synchronized, bus termination occurs two cycles after LGTA assertion, so in case of read
cycle, the device still must drive data as long as LOE is asserted.
The user selects whether transfer acknowledge is generated internally or externally (LGTA) by
programming ORn[SETA]. Asserting LGTA always terminates an access, even if ORn[SETA] = 0
(internal transfer acknowledge generation), but it is the only means by which an access can be
terminated if ORn[SETA] = 1. The timing of LGTA is illustrated by the example in Figure 13-32.
Figure 13-32. External Termination of GPCM Access
13.4.2.4
Boot Chip-Select Operation
Boot chip-select operation allows address decoding for a boot ROM before system initialization.
LCS0 is the boot chip-select output; its operation differs from other external chip-select outputs
after a system reset. When the core begins accessing memory after system reset, LCS0 is asserted
for every local bus access until BR0 or OR0 is reconfigured.
The boot chip-select also provides a programmable port size, which is configured during reset. The
boot chip-select does not provide write protection. LCS0 operates this way until the first write to
OR0 and it can be used as any other chip-select register after the preferred address range is loaded
into BR0. After the first write to OR0, the boot chip-select can be restarted only with a hardware
reset. Table 13-27 describes the initial values of the boot bank in the memory controller.
LCLK
LAD
LALE
LCSn
LBCTL
Address
A
Latched Address
TA
LOE
LGTA
Read Data



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