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MPC8540 Datasheet(PDF) 555 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 555 Page - Freescale Semiconductor, Inc

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Functional Description
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
13-51
13.4.3 SDRAM Machine
The LBC provides an SDRAM interface (machine) for the local bus. The machine provides the
control functions and signals for Intel PC133 and JEDEC-compliant SDRAM devices. Each bank
can control an SDRAM device on the local bus.
13.4.3.1
Supported SDRAM Configurations
The memory controller supports any SDRAM configuration with the restrictions that all SDRAM
devices that reside on the bus should have the same port size and timing parameters (as defined in
LSDMR). Figure 13-33 shows an example connection between the LBC and a 32-bit SDRAM
device with 12 address lines. Note that address signals A[4:0] of the SDRAM connect directly to
LA[27:31], address pin A10 connects to the LBCs dedicated LSDA10 signal, while the remaining
address bits (except A10) are latched from LAD[20:26].
Table 13-27. Boot Bank Field Values after Reset
Register
Field
Setting
BR0
BA
XBA
PS
DECC
WP
MSEL
ATOM
V
0000_0000_0000_0000_0
00
From pin during reset.
00
0
000
00
1
OR0
AM
XAM
BCTLD
CSNT
ACS
XACS
SCY
SETA
TRLX
EHTR
EAD
0000_0000_0000_0000_0
00
0
1
11
1
1111
0
1
1
1



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