MPC8540 datasheet(556/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-52

Freescale Semiconductor

Local Bus Controller

Figure 13-33. Connection to a 32-Bit SDRAM with 12 Address Lines

13.4.3.2

SDRAM Power-On Initialization

Following a system reset, initialization software must set up the programmable parameters in the

memory controller banks registers (ORn, BRn, LSDMR). After all memory parameters are

configured, system software should execute the following initialization sequence for each

SDRAM device.

•

Issue a PRECHARGE-ALL-BANKS command

•

Issue eight AUTO-REFRESH commands

•

Issue a MODE-SET command to initialize the mode register

The initial commands are executed by setting LSDMR[OP] and accessing the SDRAM with any

write that hits the relevant bank.

Note that software should ensure that no memory operations begin until this process completes.

13.4.3.3 Intel PC133 and JEDEC-Standard SDRAM Interface Commands

The SDRAM machine performs all accesses to SDRAM by using Intel PC133 and

JEDEC-standard SDRAM interface commands. The SDRAM device samples the command and

LSDA10

LSDDQM[0:3]

LCS1

LAD[0:31]

SDRAM

Local Bus

Memory Address

LALE

LSDWE

32-Bit Port Size

LSDRAS

LSDCAS

Controller

LCKE

LCLK

LA[27:29]

RAS

CAS

DQM[3:0]

A10

A[11,9:3]

DQ[31:0]

CLK

CKE

A[2:0]

LAD[18,20:26]

Memory Data

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