MPC8540 datasheet(552/1302 Pages) FREESCALE

552 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-48

Freescale Semiconductor

Local Bus Controller

Figure 13-29. GPCM Relaxed Timing Write (XACS = 0, ACS = 00, SCY = 1, CSNT = 1,

TRLX = 1, CLKDIV = 4 or 8)

13.4.2.2.4 Output Enable (LOE) Timing

The timing of the LOE is affected only by TRLX. It always asserts and negates on the rising edge

of the bus clock. LOE asserts either on the rising edge of the bus clock after LCSn is asserted or

coinciding with LCSn (if XACS = 1 and ACS = 10 or 11). Accordingly, assertion of LOE can be

delayed (along with the assertion of LCSn) by programming TRLX = 1. LOE negates on the rising

clock edge coinciding with LCSn negation

13.4.2.2.5 Extended Hold Time on Read Accesses

Slow memory devices that take a long time to disable their data bus drivers on read accesses should

choose some combination of ORn[TRLX,EHTR]. Any access following a read access to the

slower memory bank is delayed by the number of clock cycles specified in Table 13-6 in addition

to any existing bus turnaround cycle. The final bus turnaround cycle is automatically inserted by

the LBC for reads, regardless of the setting of ORn[EHTR].

LCLK

LAD

LALE

LCSn

LBCTL

Address

Latched Address

LWEn

Write Data

LOE

CSNT = 1

SCY = 1, TRLX = 1

MPC8540 Datasheet(PDF) 552 Page - Freescale Semiconductor, Inc