MPC8540 datasheet(539/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-35

13.4.1.2

External Address Latch Enable Signal (LALE)

The local bus uses a multiplexed address/data bus. Therefore the LBC must distinguish between

address and data phases, which take place on the same bus (LAD[0:31] pins). The LALE signal,

when asserted, signifies an address phase during which the LBC drives the memory address on the

LAD[0:31] pins. An external address latch uses this signal to capture the address and provide it to

the address pins of the memory or peripheral device. When LALE is negated, LAD[0:31] then

serves as the (bi-directional) data bus for the access. Any address phase initiates the assertion of

LALE, which has a programmable duration of between 1 and 4 bus clock cycles.

To ensure adequate hold time on the external address latch, LALE negates earlier than the address

changes on LAD[0:31] during address phases. By default, LALE negates earlier by an amount

equal to the platform clock period (which, divided by LCRR[CLKDIV], yields the bus clock). For

example, if LBC is operating at 333 MHz internally, then an additional 3 ns of address hold time

is introduced. However, when LCRR[CLKDIV] = 2 and the LCLK frequency exceeds 100 MHz,

the duration of the shortened LALE pulse may not meet the minimum latch enable pulse width

specifications of some latches. In such cases, setting LBCR[AHD] = 1 increases the LALE pulse

width by half of one platform clock cycle, and decreases the address hold time by the same

amount. At 333 MHz and with LCRR[CLKDIV] = 2, the duration of LALE would then be 4.5 ns,

with 1.5 ns of hold time. If both longer hold time and longer LALE pulse duration are needed, then

the address phase can be extended using the ORn[EAD] and LCRR[EADC] fields, and the

LBCR[AHD] bit can be left at 0. However, this will add latency to all address tenures.

The frequency of LALE assertion varies across the three memory controllers. For GPCM, every

assertion of LCSn is considered an independent access, and accordingly, LALE asserts prior to

each such access. For example, GPCM driving an 8-bit port would assert LALE and LCSn 32

times in order to satisfy a 32-byte cache line transfer. The SDRAM controller asserts LALE only

to initiate a burst transfer with a starting address, therefore no more than one assertion of LALE

may be required for SDRAM to transfer a 32-byte cache line through a 32-bit port. In the case of

UPM, the frequency of LALE assertion depends on how the UPM RAM is programmed. UPM

single accesses typically assert LALE once, upon commencement, but it is possible to program

UPM to assert LALE several times, and to change the values of LA[27:31] with and without LALE

being involved. In general, when using the GPCM and SDRAM controllers it is not necessary to

use LA[27:31] if a sufficiently wide latch is used to capture the entire address during LALE

phases. UPM may require LA[27:31] if the LBC is generating its own burst address sequence.

To illustrate how a large transaction is handled by the LBC, Figure 13-21 shows LBC signals for

GPCM performing a 32-byte write starting at address 0x5420. Note that during each of the 32

assertions of LALE, LA[27:31] exactly mirror LAD[27:31], but during data phases, only

LAD[0:7] and LDP[0] are driven with valid data and parity, respectively.

MPC8540 Datasheet(PDF) 539 Page - Freescale Semiconductor, Inc