MPC8540 datasheet(535/1302 Pages) FREESCALE

535 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-31

13.3.1.15 Local Bus Configuration Register (LBCR)

The local bus configuration register (LBCR) is shown in Figure 13-18.

Table 13-21 describes LBCR fields.

11 12 13

23 24

LDIS

BTCLC AHD

LPBSE EPAR

BMT

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_50D0

Figure 13-18. Local Bus Configuration Register

Table 13-21. LBCR Field Descriptions

Bits

Name

Description

LDIS

Local bus disable

0 Local bus is enabled

1 Local bus is disabled. No internal transactions will be acknowledged.

1–7

—

Reserved

8–9

BCTLC Defines the use of LBCTL

00 LBCTL is used as W/R control for GPCM or UPM accesses (buffer control).

01 LBCTL is used as LOE for GPCM accesses only.

10 LBCTL is used as LWE for GPCM accesses only.

11 Reserved.

AHD

Address hold disable. Removes part of the hold time for LAD with respect to LALE in order to lengthen

the LALE pulse

0 During address phases on the local bus, the LALE signal negates one platform clock period prior to

the address being invalidated. At 333 MHz, this provides 3 ns of additional address hold time at the

external address latch.

1 During address phases on the local bus, the LALE signal negates half of one platform clock period

prior to the address being invalidated. This halves the address hold time, but extends the latch

enable duration. This may be necessary for very high frequency designs.

11–13

—

Reserved

LPBSE Enables parity byte select on LGTA/LGPL4/LUPWAIT/LPBSE pin.

0 Parity byte select is disabled. LGTA/LGPL4/LUPWAIT/LPBSE pin is available for memory control as

LGPL4 (output) or LGTA/LUPWAIT (input).

1 Parity byte select is enabled. LGTA/LGPL4/LUPWAIT/LPBSE pin is dedicated as the parity byte

select output, and LGTA/LUPWAIT is disabled.

EPAR Determines odd or even parity. Writing the memory with EPAR = 1 and reading the memory with

EPAR = 0 generates parity errors for testing.

0 Odd parity

1 Even parity

MPC8540 Datasheet(PDF) 535 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 535 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL