MPC8540 datasheet(533/1302 Pages) FREESCALE

533 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-29

Table 13-18 describes LTEIR fields.

13.3.1.13 Transfer Error Attributes Register (LTEATR)

Figure 13-16 shows the LTEATR. After LTEATR[V] has been set, software must clear this bit to

allow LTEATR and LTEAR to update following any subsequent errors.

Table 13-18. LTEIR Field Descriptions

Bits

Name

Description

BMI

Bus monitor error interrupt enable

0 Bus monitor error reporting is disabled.

1 Bus monitor error reporting is enabled.

1—

Reserved

PARI

Parity error interrupt enable. Note that uncorrectable read errors may cause the assertion of

core_fault_in, which causes the core to generate a machine check interrupt, unless it is disabled (by

clearing HID1[RFXE]). If RFXE is zero and this error occurs, LTEDR[PARD] must be cleared and PARI

must be set to ensure that an interrupt is generated. For more information, see Section 6.10.2,

“Hardware Implementation-Dependent Register 1 (HID1).”

0 Parity error reporting is disabled.

1 Parity error reporting is enabled.

3–4

—

Reserved

WPI

Write protect error interrupt enable

0 Write protect error reporting is disabled.

1 Write protect error reporting is enabled.

6–7

—

Reserved

WARA Write-after-read atomic (WARA) error interrupt enable

0 WARA error reporting is disabled.

1 WARA error reporting is enabled.

RAWA Read-after-write atomic (RAWA) error interrupt enable

0 RAWA error reporting is disabled.

1 RAWA error reporting is enabled.

10–11

—

Reserved

CSI

Chip select error interrupt enable

0 Chip select error reporting is disabled.

1 Chip select error reporting is enabled.

13–31

—

Reserved

10 11

15 16

19 20

27 28 29 30 31

RWB

SRCID

BNK

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_50BC

Figure 13-16. Transfer Error Attributes Register (LTEATR)

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