MPC8540 datasheet(530/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-26

Freescale Semiconductor

Local Bus Controller

13.3.1.10 Transfer Error Status Register (LTESR)

The LBC has five registers for error management.

•

The transfer error status register (LTESR) indicates the cause of an error.

•

The transfer error check disable register (LTEDR) is used to enable (and disable) error

checking.

•

The transfer error check interrupt register (LTEIR) enables reporting of errors through an

interrupt.

•

The transfer error attributes register (LTEATR) captures source attributes of an error.

•

The transfer error address register (LTEAR) captures the address of a transaction that

caused an error.

LTESR, shown in Figure 13-13, is a write-one-to-clear register. Reading LTESR occurs normally;

however, write operations can clear but not set bits. A bit is cleared whenever the register is written

and the data in the corresponding bit location is a 1. For example, to clear only the write protect

error bit (LTESR[WP]) without affecting other LTESR bits, 0x0400_0000 should be written to the

Table 13-16 describes LTESR fields.

10 111213

PAR

ATMW ATMR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_50B0

Figure 13-13. Transfer Error Status Register (LTESR)

Table 13-16. LTESR Field Descriptions

Bits

Name

Description

Bus monitor time-out

0 No local bus monitor time-out occurred.

1 Local bus monitor time-out occurred. No data beat was acknowledged on the bus within

LBCR[BMT]

× 8 bus clock cycles from the start of a transaction.

1—

Reserved

PAR

Parity

0 No local bus parity error

1 Local bus parity error. LTEATR[PB] indicates the byte lane that caused the error and LTEATR[BNK]

indicates which memory controller bank was accessed.

3–4

—

Reserved

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