MPC8540 datasheet(527/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-23

Table 13-12 describes LSDMR fields.

Table 13-13. LSDMR Field Descriptions

Bits

Name

Description

0—

Reserved

RFEN

Refresh enable. Indicates that the SDRAM requires refresh services.

0 Refresh services are not required.

1 Refresh services are required.

2–4

SDRAM operation. Selects the operation that occurs when the SDRAM device is accessed.

5–7

—

Reserved

8–10

BSMA

Bank select multiplexed address line. Selects which address pins serve as the 2-bit bank-select

address for SDRAM. Note that only 4-bank SDRAMs are supported.

000 LA12:LA13

001 LA13:LA14

010 LA14:LA15

011 LA15:LA16

100 LA16:LA17

101 LA17:LA18

110 LA18:LA19

111 LA19:LA20

11–13

—

Reserved

14–16

RFCR

Refresh recovery. Sets the refresh recovery interval in bus clock cycles. Defines the earliest timing

for an ACTIVATE or REFRESH command after a REFRESH command.

000 Reserved

001 3 clocks

010 4 clocks

011 5 clocks

100 6 clocks

101 7 clocks

110 8 clocks

111 16 clocks

17–19

PRETOACT Defines the earliest timing for ACTIVATE or REFRESH command after a PRECHARGE command

(number of bus clock cycle wait states).

000 8

001 1

010 2

011 3

100 4

101 5

110 6

111 7

Value

Meaning

Use

000

Normal operation

001

Auto refresh

Initialization

010

Self refresh

Power-down mode or debug

011

Mode Register write

Initialization

100

Precharge bank

Debug

101

Precharge all banks

Initialization

110

Activate bank

Debug

111

Read/write without valid data transfer Debug

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