MPC8540 datasheet(526/1302 Pages) FREESCALE

526 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-22

Freescale Semiconductor

Local Bus Controller

Table 13-11 describes MRTPR fields.

13.3.1.6

UPM Data Register (MDR)

The memory data register (MDR), shown in Figure 13-9, contains data written to or read from the

RAM array for UPM read or write commands. MDR must be set up before issuing a write

command to the UPM.

Table 13-12 describes MDR[D].

13.3.1.7

SDRAM Machine Mode Register (LSDMR)

The local bus SDRAM mode register (LSDMR), shown in Figure 13-10, is used to configure

operations pertaining to SDRAM.

Table 13-11. MRTPR Field Descriptions

Bits

Name

Description

0–7

PTP

Refresh timers prescaler. Determines the period of the refresh timers input clock. The system clock is

divided by PTP except when the value is 0000_0000, which represents the maximum divider of 256.

8–31

—

Reserved

Reset

0000_0000_0000_0000

Offset

0x0_5088

Figure 13-9. UPM Data Register (MDR)

Table 13-12. MDR Field Description

Bits

Name

Description

0–31

The data to be read or written into the RAM array when a write or read command is supplied to the

UPM (MxMR[OP] = 01 or MxMR[OP] = 10).

4 5

7 8

10 11

13 14 15

23 24 25 26 27 28

30 31

RFEN OP

BSMA

RFCR RFCR PRETOACT ACTTORW BL

WRC

BUFCMD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_5094

Figure 13-10. SDRAM Machine Mode Register (LSDMR)

MPC8540 Datasheet(PDF) 526 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 526 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL