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MPC8540 Datasheet(PDF) 529 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 529 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definition
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
13-25
Table 13-14 describes LURT fields.
13.3.1.9
SDRAM Refresh Timer (LSRT)
The SDRAM refresh timer (LSRT), shown in Figure 13-12, generates a refresh request for all valid
banks that selected a SDRAM machine and are refresh-enabled (LSDMR[RFEN] = 1). Each time
the timer expires, all qualifying banks generate a bank staggering auto-refresh request using the
SDRAM machine.
Table 13-15 describes LSRT fields.
Table 13-14. LURT Field Descriptions
Bits
Name
Description
0–7
LURT UPM refresh timer period. Determines, along with the timer prescaler (MRTPR), the timer period
according to the following equation:
Example: For a 266-MHz system clock and a required service rate of 15.6 µs, given MRTPR[PTP] = 32,
the LURT value should be 128 decimal. 128/(266 MHz/32) = 15.4 µs, which is less than the required
service period of 15.6 µs.
Note that the reset value (0x00) sets the maximum period to 256 x MRTPR[PTP] system clock cycles.
8–31
—
Reserved
07
8
31
R
LSRT
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0x0_50A4
Figure 13-12. LSRT SDRAM Refresh Timer (LSRT)
Table 13-15. LSRT Field Descriptions
Bits
Name
Description
0–7
LSRT
SDRAM refresh timer period. Determines, along with the timer prescaler (MRTPR), the timer period
according to the following equation:
Example: For a 266-MHz system clock and a required service rate of 15.6 µs, given PTP = 32, the
LSRT value should be 128 decimal. 128/(266 MHz/32) = 15.4 µs, which is less than the required
service period of 15.6 µs.
Note that the reset value, 0x00, sets the maximum period to 256
× MRTPR[PTP] system clock cycles.
8–31
—
Reserved
TimerPeriod
LURT
Fsystemclock
MRTPR PTP
[]
----------------------------------------
⎝⎠
⎛⎞
----------------------------------------------
=
TimerPeriod
LSRT
Fsystemclock
MRTPR PTP
[]
----------------------------------------
⎝⎠
⎛⎞
----------------------------------------------
=



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