MPC8540 datasheet(531/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-27

13.3.1.11 Transfer Error Check Disable Register (LTEDR)

The transfer error check disable register (LTEDR), shown in Figure 13-14, is used to disable error

checking. Note that control of error checking is independent of control of reporting of errors

(LTEIR) through the interrupt mechanism.

Table 13-17 describes LTEDR fields.

Write protect error

0 No write protect error occurred.

1 A write was attempted to a local bus memory region that was defined as read-only in the memory

controller. Usually, in this case, a bus monitor time-out will occur (as the cycle is not automatically

terminated).

6–7

—

Reserved

8ATMW Atomic error write

0 No atomic write error occurred.

1 The subsequent write (WARA) to a memory bank did not occur within 256 bus clock cycles.

ATMR Atomic error read

0 No atomic read error occurred.

1 The subsequent read (RAWA) to a memory bank did not occur within 256 bus clock cycles.

10–11

—

Reserved

Chip select error

0 No chip select error occurred.

1 A transaction was sent to the LBC that did not hit any memory bank.

13–31

—

Reserved

BMD

PARD

WPD

WARA RAWA

CSD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_50B4

Figure 13-14. Transfer Error Check Disable Register (LTEDR)

Table 13-17. LTEDR Field Descriptions

Bits

Name

Description

BMD

Bus monitor disable

0 Bus monitor is enabled

1 Bus monitor is disabled

1—

Reserved

Table 13-16. LTESR Field Descriptions (continued)

Bits

Name

Description

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