MPC8540 datasheet(534/1302 Pages) FREESCALE

534 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-30

Freescale Semiconductor

Local Bus Controller

Table 13-19 describes LTEATR fields.

13.3.1.14 Transfer Error Address Register (LTEAR)

The transfer error address register (LTEAR) is shown in Figure 13-17.

Table 13-20 describes LTEAR[A].

Table 13-19. LTEATR Field Descriptions

Bits

Name

Description

0–2

—

Reserved

RWB

Transaction type for the error

0 The transaction for the error was a write transaction.

1 The transaction for the error was a read transaction.

4–10

—

Reserved

11–15

SRCID Captures the source of the transaction when this information is provided on the internal interface to the

LBC.

16–19

Parity error on byte. There are four parity error status bits, one per byte lane. A bit is set for the byte

that had a parity error (bit 16 represents byte 0, the most significant byte lane).

20–27

BNK

Memory controller bank. There is one error status bit per memory controller bank (bit 20 represents

bank 0). A bit is set for the local bus memory controller bank that had an error. Note that BNK is invalid

if the error was not caused by parity checks.

28–29

Extended address for the error. These bits capture the two msbs of the 34-bit address of the

transaction resulting in an error.

—

Reserved

Error attribute capture is valid. Indicates that the captured error information is valid

0 Captured error attributes and address are not valid

1 Captured error attributes and address are valid

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_50C0

Figure 13-17. Transfer Error Address Register (LTEAR)

Table 13-20. LTEAR Field Descriptions

Bits

Name

Description

0–31

Transaction address for the error. Holds the 32 lsbs of the 34-bit address of the transaction resulting

in an error.

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