MPC8540 datasheet(536/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-32

Freescale Semiconductor

Local Bus Controller

13.3.1.16 Clock Ratio Register (LCRR)

The clock ratio register sets the system (CCB) clock to LBC bus frequency ratio. It also provides

configuration bits for extra delay cycles for address and control signals.

Table 13-22 describes LCRR fields.

16–23

BMT

Bus monitor timing. Defines the bus monitor time-out period. Clearing BMT (reset value) selects the

maximum count of 2048 bus clock cycles. For non-zero values of BMT, the number of LCLK clock

cycles to count down before a time-out error is generated is given by: bus cycles = BMT x 8.

Apart from BMT = 0x00, the minimum value of BMT is 5, corresponding with 40 bus cycles. Shorter

time-outs may result in spurious errors during SDRAM operation.

24–31

—

Reserved

1314

1516

27 28

DBYP

BUFCMDC

ECL

EADC

CLKDIV

Reset

1000_0000_0000_0000_0000_0000_0000_1000

Offset

0x0_50D4

Figure 13-19. Clock Ratio Register (LCRR)

Table 13-22. LCRR Field Descriptions

Bits

Name

Description

DBYP

DLL bypass. This bit should be set when using low bus clock frequencies if the DLL is unable to

lock. When in DLL bypass mode, incoming data is captured in the middle of the bus clock cycle.

0 The DLL is enabled.

1 The DLL is bypassed.

1—

Reserved

2–3

BUFCMDC Additional delay cycles for SDRAM control signals. Defines the number of cycles to be added for

each SDRAM command when LSDMR[BUFCMD] = 1.

00 4

01 1

10 2

11 3

4–5

—

Reserved

6–7

ECL

Extended CAS latency. Determines the extended CAS latency for SDRAM accesses when

LSDMR[CL] = 00.

00 4

01 5

10 6

11 7

8–13

—

Reserved

Table 13-21. LBCR Field Descriptions (continued)

Bits

Name

Description

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