MPC8540 datasheet(537/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-33

13.4 Functional Description

The LBC allows the implementation of memory systems with very specific timing requirements.

•

The SDRAM machine provides an interface to SDRAMs using bank interleaving and

back-to-back page mode to achieve high performance through a multiplexed address/data

bus. An internal DLL for bus clock generation ensures improved data set-up margins for

board designs.

•

The GPCM provides interfacing for simpler, lower-performance memories and

memory-mapped devices. It has inherently lower performance because it does not support

bursting. For this reason, GPCM-controlled banks are used primarily for boot-loading and

access to low-performance memory-mapped peripherals.

•

The UPM supports refresh timers, address multiplexing of the external bus and generation

of programmable control signals for row address and column address strobes, to allow for

a minimal glue logic interface to DRAMs, burstable SRAMs, and almost any other kind of

peripheral. The UPM can be used to generate flexible, user-defined timing patterns for

control signals that govern a memory device. These patterns define how the external control

signals behave during a read, write, burst-read, or burst-write access. Refresh timers are

also available to periodically initiate user-defined refresh patterns.

14–15

EADC

External address delay cycles. Defines the number of cycles for the assertion of LALE. Note that

LALE negates prior to the end of the final local bus clock, as controlled by LBCR[AHD].

00 4

01 1

10 2

11 3

16–27

—

Reserved

28–31

CLKDIV

System (CCB) clock divider. Sets the frequency ratio between the system (CCB) clock and the

memory bus clock. Only the values shown in the table below are allowed.

0000–0001Reserved

0010 2

0011 Reserved

0100 4

0101–0111Reserved

1000 8

1001–1111Reserved

Table 13-22. LCRR Field Descriptions (continued)

Bits

Name

Description

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