MPC8540 datasheet(538/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-34

Freescale Semiconductor

Local Bus Controller

Figure 13-20. Basic Operation of Memory Controllers in the LBC

Each memory bank (chip select) can be assigned to any one of these three type of machines

through the machine select bits of the base register for that bank (BRn[MSEL]), as illustrated in

Figure 13-20. If a bank match occurs, the corresponding machine (GPCM, SDRAM or UPM) then

takes ownership of the external signals that control the access and maintains control until the

transaction ends.

13.4.1 Basic Architecture

The following sections describe the basic architecture of the LBC.

13.4.1.1

Address and Address Space Checking

The defined base addresses are written to the BRn registers, while the corresponding address

masks are written to the ORn registers. Each time a local bus access is requested, the internal

transaction address is compared with each bank. Addresses are decoded by comparing the 19 msbs

of the address, masked by ORn[XAM] and ORn[AM], with the base address for each bank

(BRn[XBA] and BRn[BA]). If a match is found on a memory controller bank, the attributes

defined in the BRn and ORn for that bank are used to control the memory access. If a match is

found in more than one bank, the lowest-numbered bank handles the memory access (that is, bank

0 has priority over bank 1).

Address

Comparator

Bank Select

UPM A/B/C

GPCM

MSEL

Field

Signals

Timing

Generator

MUX

Internal Memory Access Request Select

34-bit System

External Signals

SDRAM Machine

Address

32-Bit Physical

RAM Address (A)

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