MPC8540 datasheet(540/1302 Pages) FREESCALE

540 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-36

Freescale Semiconductor

Local Bus Controller

Figure 13-21. Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420

13.4.1.3

Data Transfer Acknowledge (TA)

The three memory controllers in the LBC generate an internal transfer acknowledge signal, TA, to

allow data on LAD[0:31] to be either sampled (for reads) or changed (on writes). The data

sampling/data change always occurs at the end of the bus cycle in which the LBC asserts TA

internally. In LBC debug mode, TA is also visible externally on the MDVAL pin. GPCM and

SDRAM controllers automatically generate TA according to the timing parameters programmed

for them in option and mode registers; a UPM generates TA only when a UPM pattern has the UTA

RAM word bit set. Figure 13-22 shows LALE, TA (internal), and LCSn. Note that TA and LALE

are never asserted together, and that for the duration of LALE, LCSn (or any other control signal)

remains negated or frozen.

0P(B0)

000

P(B1)P(B2)P(B29)P(B30)

P(B31)

D(B0)

D(B1)D(B2)D(B29)D(B30)

D(B31)

000

Note: All address and signal values are shown in hexadecimal.

D(Bk) = kth of 32 data bytes, P(Bk) = parity bit of kth data byte.

LCLK

LALE

LCSn

LWE

LA[27:31]

LAD[0:7]

LAD[8:31]

LDP[0]

LDP[1:3]

MPC8540 Datasheet(PDF) 540 Page - Freescale Semiconductor, Inc