MPC8540 datasheet(532/1302 Pages) FREESCALE

532 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-28

Freescale Semiconductor

Local Bus Controller

13.3.1.12 Transfer Error Interrupt Enable Register (LTEIR)

The transfer error interrupt enable register (LTEIR), shown in Figure 13-15, is used to send or

block error reporting through the LBC internal interrupt mechanism. Software should clear

pending errors in LTESR before enabling interrupts. After an interrupt has occurred, clearing

relevant LTESR error bits negates the interrupt.

PARD Parity error checking disabled. Note that uncorrectable read errors may cause the assertion of

core_fault_in, which causes the core to generate a machine check interrupt, unless it is disabled (by

clearing HID1[RFXE]). If RFXE is zero and this error occurs, PARD must be cleared and LTEIR[PARI]

must be set to ensure that an interrupt is generated. For more information, see Section 6.10.2,

“Hardware Implementation-Dependent Register 1 (HID1).”

0 Parity error checking is enabled.

1 Parity error checking is disabled.

3–4

—

Reserved

WPD

Write protect error checking disable

0 Write protect error checking is enabled.

1 Write protect error checking is disabled.

6–7

—

Reserved

WARA Write-after-read atomic (WARA) error checking disable

0 WARA error checking is enabled.

1 WARA error checking is disabled.

RAWA Read-after-write atomic (RAWA) error checking disable

0 RAWA error checking is enabled.

1 RAWA error checking is disabled.

10–11

—

Reserved

CSD

Chip select error checking disable

0 Chip select error checking is enabled.

1 Chip select error checking is disabled.

13–31

—

Reserved

BMI

PARI

WPI

WARA

RAWA

CSI

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_50B8

Figure 13-15. Transfer Error Interrupt Enable Register (LTEIR)

Table 13-17. LTEDR Field Descriptions (continued)

Bits

Name

Description

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