MPC8540 datasheet(528/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-24

Freescale Semiconductor

Local Bus Controller

13.3.1.8

UPM Refresh Timer (LURT)

The UPM refresh timer (LURT), shown in Figure 13-11, generates a refresh request for all valid

banks that selected a UPM machine and are refresh-enabled (MxMR[RFEN] = 1). Each time the

timer expires, a qualified bank generates a refresh request using the selected UPM. The qualified

banks rotate their requests.

20–22

ACTTORW Defines the earliest timing for READ/WRITE command after an ACTIVATE command (number of

bus clock cycle wait states).

000 8

001 Reserved

010 2

011 3

100 4

101 5

110 6

111 7

Sets the burst length for SDRAM accesses.

0 SDRAM burst length is 4. Use this value if the device port size is16.

1 SDRAM burst length is 8. Use this value if the device port size is 32 or 8.

24–25

—

Reserved

26–27

WRC

Write recovery time. Defines the earliest timing for PRECHARGE command after the last data is

written to the SDRAM.

00 4

01 Reserved

10 2

11 3

—

Reserved

BUFCMD

Control line assertion timing. If external buffers are placed on the control lines going to both the

SDRAM and address lines, setting BUFCMD causes all SDRAM control lines except LCSn,

LCKE, LALE and LSDDQM[0:3] to be asserted for LCRR[BUFCMDC] cycles, instead of one.

0 Normal timing for the control lines

1 All control lines except LCSn are asserted for the number of cycles specified by

LCRR[BUFCMDC].

30–31

CAS latency. Defines the timing for first read data after SDRAM samples a column address.

00 Extended CAS latency. According to LCRR[ECL]. See Table 13-22 on page 13-32.

01 1

10 2

11 3

LURT

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_50A0

Figure 13-11. UPM Refresh Timer (LURT)

Table 13-13. LSDMR Field Descriptions (continued)

Bits

Name

Description

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