MPC8540 datasheet(524/1302 Pages) FREESCALE

524 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-20

Freescale Semiconductor

Local Bus Controller

5–7

Address multiplex size. Determines how the address of the current memory cycle can be output on the

address pins. This field is needed when interfacing with devices requiring row and column addresses

multiplexed on the same pins.

8–9

Disable timer period. Guarantees a minimum time between accesses to the same memory bank

controlled by UPMn. The disable timer is turned on by the TODT bit in the RAM array word, and when

expired, the UPMn allows the machine access to handle a memory pattern to the same bank. Accesses

to a different bank by the same UPMn is also allowed. To avoid conflicts between successive accesses

to different banks, the minimum pattern in the RAM array for a request serviced, should not be shorter

than the period established by DS.

00 1-bus clock cycle disable period

01 2-bus clock cycle disable period

10 3-bus clock cycle disable period

11 4-bus clock cycle disable period

10–12

G0CL General line 0 control. Determines which logical address line can be output to the LGPL0 pin when the

UPMn is selected to control the memory access.

000 A12

001 A11

010 A10

011 A9

100 A8

101 A7

110 A6

111 A5

GPL4 LGPL4 output line disable. Determines how the LGPL4/LUPWAIT pin is controlled by the

corresponding bits in the UPMn array. See Table 13-30 on page 13-69.

Table 13-10. MxMR Field Descriptions (continued)

Bits

Name

Description

Value LA0–LA15

LA16

LA17

LA18

LA19–LA28

LA29

LA30

LA31

000

A10

A11–A20

A21

A22

A23

001

A10–A19

A20

A21

A22

010

A9–A18

A19

A20

A21

011

A8–A17

A18

A19

A20

100

A7–A16

A17

A18

A19

101

A6–A15

A16

A17

A18

110

Reserved

111

Reserved

Value

LGPL4/LUPWAIT

Pin Function

Interpretation of UPM Word Bits

G4T1/DLT3

G4T3/WAEN

LGPL4 (output)

G4T1

G4T3

LUPWAIT (input)

DLT3

WAEN

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