MPC8540 datasheet(521/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-17

13.3.1.2.4 Option Registers (ORn)—SDRAM Mode

Figure 13-5 shows the bit fields for ORn when the corresponding BRn[MSEL] selects the

SDRAM machine.

BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.

0 LBCTL is asserted upon access to the current memory bank.

1 LBCTL is not asserted upon access to the current memory bank.

20–22

—

Reserved

Burst inhibit. Indicates if this memory bank supports burst accesses.

0 The bank supports burst accesses.

1 The bank does not support burst accesses. The selected UPM executes burst accesses as a series

of single accesses.

24–28

—

Reserved

TRLX

Timing relaxed. Works in conjunction with EHTR to extend hold time on read accesses.

EHTR

Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a

read access from the current bank and the next access.

TRLX EHTR

Meaning

The memory controller generates normal timing. No additional cycles are inserted.

1 idle clock cycle is inserted.

4 idle clock cycles are inserted.

8 idle clock cycles are inserted.

EAD

External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).

0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)

1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by

LCRR[EADC]).

1617 1819

2122 23

27 28

COLS

ROWS

PMSEL

EAD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_5004 (OR0); 0x0_500c (OR1); 0x0_5014 (OR2); 0x0_501c (OR3);

0x0_5024 (OR4); 0x0_502c (OR5); 0x0_5034 (OR6); 0x0_503c (OR7);

Figure 13-5. Option Registers (ORn) in SDRAM Mode

Table 13-7. ORn

—UPM Field Descriptions (continued)

Bits

Name

Description

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