MPC8540 datasheet(518/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-14

Freescale Semiconductor

Local Bus Controller

13.3.1.2.2 Option Registers (ORn)—GPCM Mode

Figure 13-3 shows the bit fields for ORn when the corresponding BRn[MSEL] selects the GPCM

machine.

Table 13-6 describes ORn fields for GPCM mode.

016

17 18

21 22

—

BCTLD CSNT ACS XACS

SCY

SETA TRLX EHTR EAD

Reset

0000_0000_0000_0000_0000_1111_1111_0111 1 (OR0);

0000_0000_0000_0000_0000_0000_0000_0000 (all others)

Offset

0x0_5004 (OR0); 0x0_500C (OR1); 0x0_5014 (OR2); 0x0_501C (OR3);

0x0_5024 (OR4); 0x0_502C (OR5); 0x0_5034 (OR6); 0x0_503C (OR7);

1 OR0 has this value set during reset (GPCM is the default control machine for all banks coming out of reset). All other

option registers have all bits cleared.

Figure 13-3. Option Registers (ORn) in GPCM Mode

Table 13-6. ORn

—GPCM Field Descriptions

Bits

Name

Description

0–16

GPCM address mask. Masks corresponding BRn bits. Masking address bits independently allows

external devices of different size address ranges to be used. Address mask bits can be set or cleared

in any order in the field, allowing a resource to reside in more than one area of the address map.

0 Corresponding address bits are masked.

1 Corresponding address bits are used in the comparison between base and transaction addresses.

17–18

—

Reserved

BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.

0 LBCTL is asserted upon access to the current memory bank.

1 LBCTL is not asserted upon access to the current memory bank.

CSNT

Chip select negation time. Determines when LCSn and LWE are negated during an external memory

write access handled by the GPCM, provided that ACS

≠ 00 (when ACS = 00, only LWE is affected

by the setting of CSNT). This helps meet address/data hold times for slow memories and peripherals.

0LCSn and LWE are negated normally.

1LCSn and LWE are negated earlier depending on the value of LCRR[CLKDIV].

LCRR[CLKDIV]

CSNT

Meaning

LCSn and LWE are negated normally.

4 or 8

LCSn and LWE are negated quarter of a bus clock cycle earlier.

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