MPC8540 datasheet(516/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-12

Freescale Semiconductor

Local Bus Controller

13.3.1.2

Option Registers (OR0–OR7)

The ORn registers define the sizes of memory banks and access attributes. The ORn attribute bits

support the following three modes of operation as defined by BRn[MSEL].

•

GPCM mode

•

UPM mode

•

SDRAM mode

The ORn registers are interpreted differently depending on which of the three machine types is

selected for that bank.

Write protect

0 Read and write accesses are allowed.

1 Only read accesses are allowed. The memory controller does not assert LCSn on write cycles to this

memory bank. WP is set (if enabled) if a write to this memory bank is attempted, and a local bus error

interrupt is generated (if enabled), terminating the cycle.

24–26 MSEL Machine select. Specifies the machine to use for handling memory operations.

000 GPCM (reset value)

001 Reserved

010 Reserved

011 SDRAM

100 UPMA

101 UPMB

110 UPMC

111 Reserved

—

Reserved

28–29 ATOM Atomic operation. Writes (reads) to the address space handled by the memory controller bank reserve

the selected memory bank for the exclusive use of the accessing device. The reservation is released

when the device performs a read (write) operation to this memory controller bank. If a subsequent read

(write) request to this memory controller bank is not detected within 256 bus clock cycles of the last

write (read), the reservation is released and an atomic error is reported (if enabled).

00 The address space controlled by this bank is not used for atomic operations.

01 Read-after-write-atomic (RAWA)

10 Write-after-read-atomic (WARA)

11 Reserved

—

Reserved

Valid bit. Indicates that the contents of the BRn and ORn pair are valid. LCSn does not assert unless

V is set (an access to a region that has no valid bit set may cause a bus time-out). After a system reset,

only BR0[V] is set.

0 This bank is invalid.

1 This bank is valid.

Table 13-4. BRn Field Descriptions (continued)

Bits

Name

Description

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