MPC8540 datasheet(514/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-10

Freescale Semiconductor

Local Bus Controller

13.3.1 Register Descriptions

This section provides a detailed description of the LBC configuration, status, and control registers

with detailed bit and field descriptions.

Address offsets in the LBC address range that are not defined in Table 13-3 should not be accessed

for reading or writing. Similarly, only zero should be written to reserved bits of defined registers,

as writing ones can have unpredictable results in some cases.

0x0_5004

OR0—Options register 0

R/W

0x0000_0FF7

13.3.1.2/13-12

0x0_500C

OR1—Options register 1

0x0000_0000

0x0_5014

OR2—Options register 2

0x0_501C

OR3—Options register 3

0x0_5024

OR4—Options register 4

0x0_502C

OR5—Options register 5

0x0_5034

OR6—Options register 6

0x0_503C

OR7—Options register 7

0x0_5068

MAR—UPM address register

R/W

0x0000_0000

13.3.1.3/13-18

0x0_5070

MAMR—UPMA mode register

R/W

0x0000_0000

13.3.1.4/13-19

0x0_5074

MBMR—UPMB mode register

R/W

0x0000_0000

13.3.1.4/13-19

0x0_5078

MCMR—UPMC mode register

R/W

0x0000_0000

13.3.1.4/13-19

0x0_5084

MRTPR—Memory refresh timer prescaler register

R/W

0x0000_0000

13.3.1.5/13-21

0x0_5088

MDR—UPM data register

R/W

0x0000_0000

13.3.1.6/13-22

0x0_5094

LSDMR—SDRAM mode register

R/W

0x0000_0000

13.3.1.7/13-22

0x0_50A0

LURT—UPM refresh timer

R/W

0x0000_0000

13.3.1.8/13-24

0x0_50A4

LSRT—SDRAM refresh timer

R/W

0x0000_0000

13.3.1.9/13-25

0x0_50B0

LTESR—Transfer error status register

Read/Bit reset

0x0000_0000

13.3.1.10/13-26

0x0_50B4

LTEDR—Transfer error disable register

R/W

0x0000_0000

13.3.1.11/13-27

0x0_50B8

LTEIR—Transfer error interrupt register

R/W

0x0000_0000

13.3.1.12/13-28

0x0_50BC

LTEATR—Transfer error attributes register

R/W

0x0000_0000

13.3.1.13/13-29

0x0_50C0

LTEAR—Transfer error address register

R/W

0x0000_0000

13.3.1.14/13-30

0x0_50D0

LBCR—Configuration register

R/W

0x0000_0000

13.3.1.15/13-31

0x0_50D4

LCRR—Clock ratio register

R/W

0x8000_0008

13.3.1.16/13-32

1 Port size for BR0 is configured from external pins during reset, hence ‘nn’ is either 0x08, 0x10, or 0x18.

Table 13-3. Local Bus Controller Memory Map (continued)

Address Offset

Use

Access

Reset

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