MPC8540 datasheet(511/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-7

LSDCAS/

LGPL3

O SDRAM CAS/General-purpose line 3

State

Meaning

Asserted/Negated—In SDRAM mode, drives the column address strobe (CAS).

One of six general-purpose signals when in UPM mode, and drives a value programmed

in the UPM array.

LGTA/

LGPL4/

LUPWAIT/

LPBSE

I/O GPCM transfer acknowledge/General-purpose line 4/UPM wait/parity byte select

State

Meaning

Asserted/Negated—Input in GPCM mode used for transaction termination. It may also be

configured as one of six general-purpose output signals when in UPM mode or as an

input to force the UPM controller to wait for the memory/device.

When configured as LPBSE, it disables any use in GPCM or UPM modes. Because

systems that use read-modify-write parity require an additional memory device, they must

generate a byte-select like a normal data device. ANDing LBS[0:3] through external logic

to achieve the logical function of this byte-select adds a delay to the byte-select path that

can affect memory access timing. The LBC provides this optional byte-select pin that is

an internal AND of the four (active low) byte selects, allowing glueless, faster connection

to RMW-parity devices.

LGPL5

O General-purpose line 5

State

Meaning

Asserted/Negated—One of six general-purpose signals when in UPM mode, and drives a

value programmed in the UPM array.

LBCTL

O Data buffer control. The memory controller activates LBCTL for the local bus when a GPCM- or

UPM-controlled bank is accessed. Access to an SDRAM machine-controlled bank does not activate the

buffer control. Buffer control is disabled by setting ORn[BCTLD].

State

Meaning

Asserted/Negated—The LBCTL pin normally functions as a write/read control for a bus

transceiver connected to the LAD lines. Note that an external data buffer must not drive

the LAD lines in conflict with the LBC when LBCTL is high, because LBCTL remains high

after reset and during address phases.

LA[27:31]

O Local bus nonmultiplexed address lsbs. All bits driven on LA[27:31] are defined for 8-bit port sizes. For

32-bit port sizes, LA[30:31] are don’t cares; for 16-bit port sizes LA31 is a don’t care.

State

Meaning

Asserted/Negated—Although the LBC shares an address and data bus, up to five lsbs of the

RAM address always appear on the dedicated address pins, LA[27:31]. These may be

used, unlatched, in place of LAD[27:31] to connect the five lsbs of the address for address

phases. For some RAM devices, such as fast-page DRAM, LA[27:31] serve as the

column address offset during a burst access.

Table 13-2. Local Bus Controller Detailed Signal Descriptions (continued)

Signal

I/O

Description

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