MPC8540 datasheet(508/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-4

Freescale Semiconductor

Local Bus Controller

13.1.3.1

LBC Bus Clock and Clock Ratios

The LBC supports ratios of 2, 4, and 8 between the faster system (CCB) clock and the slower

external bus clock (LCLK[0:2]). This ratio is software programmable through the clock ratio

clock, CLKDIV also affects the resolution of signal timing shifts in GPCM mode and the

interpretation of UPM array words in UPM mode. The bus clock is driven identically onto pins,

LCLK[0:2], to allow the clock load to be shared equally across a pair of signal nets, thereby

enhancing the edge rates of the bus clock.

13.1.3.2

Source ID Debug Mode

In debug mode, the LBC provides the ID of a transaction source on external device pins. This

mode is enabled on power-on reset, as described in Section 20.4.4, “Local Bus Interface Debug.”

When placed in this mode, the 5-bit internal ID of the current transaction source appears on

MSRCID[0:4] whenever valid address or data is available on the LBC external pins. The reserved

value of 0x1F, which indicates invalid address or data, appears on the source ID pins at all other

times. The combination of a valid source ID (any value except 0x1F) and the value of external

address latch enable (LALE) and data valid (MDVAL) facilitate capturing useful debug data as

follows:

•

If a valid source ID is detected on MSRCID[0:4] and LALE is asserted, a valid full 32-bit

address may be latched from LAD[0:31]. Note that in SDRAM mode the address vector

contains the full address as {row, bank, column, lsbs} where row corresponds to the same

row address for the given column address and lsbs are the unconnected lsbs of the address

for a given port size.

•

If a valid source ID is detected on MSRCID[0:4] and MDVAL is asserted, valid data may

be latched from LAD[0:31].

13.1.4 Power-Down Mode

The LBC can enter a power-down mode when the system stops the internal (system) clock to the

block by using a handshake protocol initiated by the DEVDISR[LBC] setting in the global utilities

block. On entering power-down mode, the LBC places any SDRAM devices, if used, in

self-refresh mode before the bus clock is stopped. The LBC also allows the DLL sufficient time

to recover following the reapplication of the system clock.

13.1.5 References

•

MPC8260 PowerQUICC II Family Reference Manual, Chapters 4, 6, and 10 (order no.

MPC8260UM).

MPC8540 Datasheet(PDF) 508 Page - Freescale Semiconductor, Inc