MPC8540 datasheet(506/1302 Pages) FREESCALE

506 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-2

Freescale Semiconductor

Local Bus Controller

13.1.1 Overview

The main component of the LBC is its memory controller, which provides a seamless interface to

many types of memory devices and peripherals. The memory controller is responsible for

controlling eight memory banks shared by a high performance SDRAM machine, a GPCM, and

up to three UPMs. As such, it supports a minimal glue logic interface to synchronous DRAM

(SDRAM), SRAM, EPROM, flash EPROM, burstable RAM, regular DRAM devices, extended

data output DRAM devices, and other peripherals. The external address latch signal (LALE)

allows multiplexing of addresses with data signals to reduce the device pin count.

The LBC also includes a number of data checking and protection features such as data parity

generation and checking, write protection and a bus monitor to ensure that each bus cycle is

terminated within a user-specified period.

13.1.2 Features

The LBC main features are as follows:

•

Memory controller with eight memory banks

— 34-bit address decoding with mask

— Variable memory block sizes (32 Kbytes to 4 Gbytes)

— Selection of control signal generation on a per-bank basis

— Data buffer controls activated on a per-bank basis

— Up to 256-byte bursts, arbitrarily aligned

— Automatic segmentation of large transactions

— Odd/even parity checking including read-modify-write (RMW) parity for single

accesses

— Write-protection capability

— Atomic operation

— Parity byte-select

•

SDRAM machine

— Provides the control functions and signals for glueless connection to JEDEC-compliant

SDRAM devices

— Supports up to four concurrent open pages per device

— Supports SDRAM port size of 32, 16, and 8 bits

— Supports external address and/or command lines buffering

MPC8540 Datasheet(PDF) 506 Page - Freescale Semiconductor, Inc