MPC8540 datasheet(503/1302 Pages) FREESCALE

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DUART Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

12-25

12.4.5.3

Interrupt Control Logic

An interrupt is active when DUART interrupt ID register bit 0 (UIIR[0]), is cleared. The interrupt

enable register (UIER) is used to mask specific interrupt types. For more details refer to the

description of UIER in Section 12.3.1.4, “Interrupt Enable Register (UIER).”

When the interrupts are disabled in UIER, polling software can not use UIIR[0] to determine

whether the UART is ready for service. The software must monitor the appropriate bits in the line

status (ULSR) and/or the MODEM status (UMSR) registers. UIIR[0] can be used for polling if the

interrupts are enabled in UIER.

12.5 DUART Initialization/Application Information

The following requirements must be met for DUART accesses:

•

All DUART registers must be mapped to a cache-inhibited area.

•

All DUART registers are 1 byte wide. Reads and writes to these registers must be byte-wide

operations.

A system reset puts the DUART registers to a default state. Before the interface can transfer serial

data, the following initialization steps are recommended:

1. Update the programmable interrupt controller (PIC) DUART channel interrupt vector

source registers.

2. Set data attributes and control bits in the ULCR, UFCR, UAFR, UMCR, UDLB, and

UDMB.

3. Set the data attributes and control bits of the external MODEM or peripheral device.

4. Set the interrupt enable register (UIER).

5. To start a write transfer, write to the UTHR.

6. Poll UIIR if the interrupts generated by the DUART are masked.

MPC8540 Datasheet(PDF) 503 Page - Freescale Semiconductor, Inc