MPC8540 datasheet(499/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

12-21

Figure 12-16. UART Bus Interface Transaction Protocol Example

A standard UART bus transfer is composed of either three or four parts:

•

START bit

•

Data transfer bits (least-significant bit is first data bit on the bus)

•

Parity bit (optional)

•

STOP bits

An internal logic sample signal, rxcnt, uses the frequency of the baud-rate generator to drive the

bits on SOUT.

The following sections describe the four components of the serial interface, the baud-rate

generator, local loop-back mode, different errors, and FIFO mode.

12.4.1.1

START Bit

A write to the transmitter holding register (UTHR) generates a START bit on the SOUT signal.

Figure 12-16 shows that the START bit is defined as a logic 0. The START bit denotes the

beginning of a new data transfer which is limited to the bit length programmed in the UART line

control register (ULCR).When the bus is idle, SOUT is high.

12.4.1.2

Data Transfer

Each data transfer contains 5–8 bits of data. The ULCR data bit length for the transmitter and

receiver UART devices must agree before a transfer begins; otherwise, a parity or framing error

may occur. A transfer begins when UTHR is written. At that time a START bit is generated

followed by 5–8 of the data bits previously written to the UTHR. The data bits are driven from the

least significant to the most significant bits. After the parity and STOP bits, a new data transfer can

begin if new data is written to the UTHR.

234

567

D6 D5 D4 D3 D2

D1 D0 PTY

D6 D5 D4 D3 D2

D1 D0 PTY

rxcnt

SOUT1

START

STOP bits

Optional

Data bits

STOP bits

Two 7-bit data transmissions with parity and 2-bit STOP transactions

even/odd parity

START

Optional

even/odd parity

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