MPC8540 datasheet(498/1302 Pages) FREESCALE

498 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

12-20

Freescale Semiconductor

DUART

12.4 Functional Description

The communication channel provides a full-duplex asynchronous receiver and transmitter using

an operating frequency derived from the CCB clock signal.

The transmitter accepts parallel data with a write access to the transmitter holding register

(UTHR). In FIFO mode, the data is placed directly into an internal transmitter shift register, or into

the transmitter FIFO—see Section 12.4.5, “FIFO Mode.” The transmitting registers convert the

data to a serial bit stream, by inserting the appropriate START, STOP, and optional parity bits.

Finally, the registers output a composite serial data stream on the channel transmitter serial data

output (SOUT). The transmitter status may be polled or interrupt-driven.

The receiver accepts serial data on the channel receiver serial data input (SIN), converts the data

into parallel format, and checks for START, STOP, and parity bits. In FIFO mode, the receiver

removes the START, STOP, and parity bits and then transfers the assembled character from the

receiver buffer, or receiver FIFO. This transfer occurs in response to a read of the UART receiver

buffer register (URBR). The receiver status may be polled or interrupt driven.

12.4.1 Serial Interface

The UART bus is a serial, full-duplex, point-to-point bus as shown in Figure 12-16. Therefore,

only two devices are attached to the same signals and there is no need for address or arbitration

bus cycles.

Table 12-24. UDSR[RXRDY] Cleared

DMS FEN

DMA Mode

Meaning

RXRDY is cleared when there is at least one character in the receiver FIFO or URBR.

RXRDY is cleared when the trigger level or a time-out has been reached. RXRDY remains

cleared until the receiver FIFO is empty.

MPC8540 Datasheet(PDF) 498 Page - Freescale Semiconductor, Inc