MPC8540 datasheet(494/1302 Pages) FREESCALE

494 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

12-16

Freescale Semiconductor

DUART

12.3.1.10 MODEM Status Registers (UMSR0, UMSR1)

The UMSRs track the status of the MODEM (or external peripheral device) clear to send (CTS)

signal for the corresponding UART.

Figure 12-12 shows the bits in the UMSRs.

Framing error

0 This bit is cleared when ULSR is read or when a new character is loaded into the URBR from the

receiver shift register.

1 Invalid STOP bit for receive data (only the first STOP bit is checked). In FIFO mode, this bit is set when

the character that detected a framing error is encountered in the FIFO (that is the character at the top

of the FIFO). An attempt to resynchronize occurs after a framing error. The UART assumes that the

framing error (due to a logic 0 being read when a logic 1 (STOP) was expected) was due to a STOP

bit overlapping with the next START bit, so it assumes this logic 0 sample is a true START bit and then

will receive the following new data.

Parity error

0 This bit is cleared when ULSR is read or when a new character is loaded into the URBR.

1 Unexpected parity value encountered when receiving data. In FIFO mode, the character with the error

is at the top of the FIFO.

Overrun error

0 This bit is cleared when ULSR is read.

1 Before the URBR is read, the URBR was overwritten with a new character. The old character is loss.

In FIFO mode, the receiver FIFO is full (regardless of the receiver FIFO trigger level setting) and a

new character has been received into the internal receiver shift register. The old character was

overwritten by the new character. Data in the receiver FIFO was not overwritten.

Data ready

0 This bit is cleared when URBR is read or when all of the data in the receiver FIFO is read.

1 A character has been received in the URBR or the receiver FIFO.

R—

CTS

—

DCTS

Reset

0x00

Offset

0x0_4506, 0x0_4606

Figure 12-12. Modem Status Register (UMSR)

Table 12-16. ULSR Field Definitions (continued)

Bits Name

Description

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