MPC8540 datasheet(491/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

12-13

Figure 12-9 shows the bits in the ULCRs.

Table 12-13 describes the fields of the ULCRs.

012

3456

DLAB

EPS

PEN

NSTB

WLS

Reset

0x00

Offset

0x0_4503, 0x0_4603

Figure 12-9. Line Control Register (ULCR)

Table 12-13. ULCR Field Definitions

Bits Name

Description

DLAB Divisor latch access bit

0 Access to all registers except UDLB, UAFR, and UDMB

1 Ability to access divisor latch least and most significant byte registers and alternate function register

(UAFR)

Set break

0 Send normal UTHR data onto the serial output (SOUT) signal

1 Force logic 0 to be on the SOUT signal. Data in the UTHR is not affected

Stick parity

0 Stick parity is disabled.

1 If PEN = 1 and EPS = 1, space parity is selected. And if PEN = 1 and EPS = 0, mark parity is selected.

EPS

Even parity select. See Table 12-14 for more information.

0 If PEN = 1 and SP = 0, odd parity is selected.

1 If PEN = 1 and SP = 0, even parity is selected.

PEN

Parity enable

0 No parity generation and checking

1 Generate parity bit as a transmitter, and check parity as a receiver

NTSB Number of STOP bits

0 One STOP bit is generated in the transmitted data.

1 When a 5-bit data length is selected, 1 ½ STOP bits are generated. When either a 6-, 7-, or 8-bit word

length is selected, two STOP bits are generated.

6–7

WLS

Word length select. Number of bits that comprise the character length. The word length select values are

as follows:

00 5 bits

01 6 bits

10 7 bits

11 8 bits

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