MPC8540 datasheet(487/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

12-9

3. The result from step two is multiplied by 100 to calculate the final percent error. The result

is calculated in absolute value (no negative numbers).

These steps can be described with the following equation:

Percent error value = (1 – AFI/ICF)

× 100

12.3.1.4

Interrupt Enable Register (UIER)

The UIER gives the user the ability to mask specific UART interrupts to the MPC8540

programmable interrupt controller (PIC).

Figure 12-6 shows the bits in the UIER.

Table 12-9 describes the fields of UIER.

456

EMSI

ERLSI

ETHREI

ERDAI

Reset

0x00

Offset

0x0_4501, 0x0_4601

Figure 12-6. Interrupt Enable Register (UIER)

Table 12-9. UIER Field Definitions

Bits

Name

Description

0–3

—

Reserved

EMSI

Enable MODEM status interrupt

0 Mask interrupts caused by UMSR[DCTS] being set

1 Enable and assert interrupts when the clear-to-send bit in the UART MODEM status register

(UMSR) changes state

ERLSI

Enable receiver line status interrupt

0 Mask interrupts when ULSR’s overrun, parity error, framing error or break interrupt bits are set

1 Enable and assert interrupts when ULSR’s overrun, parity error, framing error or break interrupt bits

are set

ETHREI Enable transmitter holding register empty interrupt

0 Mask interrupt when ULSR[THRE] is set

1 Enable and assert interrupts when ULSR[THRE] is set

ERDAI

Enable received data available interrupt

0 Mask interrupt when new receive data is available or receive data time out has occurred

1 Enable and assert interrupts when a new data character is received from the external device and/or

a time-out interrupt occurs in the FIFO mode

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