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MPC8540 Datasheet(PDF) 483 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 483 Page - Freescale Semiconductor, Inc |
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483 / 1302 page  Memory Map/Register Definition MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 12-5 contains detailed information about each register. Undefined byte address spaces within offset 0x000–0xFFF are reserved. Table 12-3. DUART Register Summary Offset Register Access Reset Section/Page 0x0_4500 URBR—ULCR[DLAB] = 0 UART0 receiver buffer register R 0x00 12.3.1.1/12-6 0x0_4500 UTHR—ULCR[DLAB] = 0 UART0 transmitter holding register W 0x00 12.3.1.2/12-6 0x0_4500 UDLB—ULCR[DLAB] = 1 UART0 divisor least significant byte register R/W 0x00 12.3.1.3/12-7 0x0_4501 UIER—ULCR[DLAB] = 0 UART0 interrupt enable register R/W 0x00 12.3.1.4/12-9 0x0_4501 UDMB—ULCR[DLAB] = 1 UART0 divisor most significant byte register R/W 0x00 12.3.1.3/12-7 0x0_4502 UIIR—ULCR[DLAB] = 0 UART0 interrupt ID register R 0x01 12.3.1.5/12-10 0x0_4502 UFCR—ULCR[DLAB] = 0 UART0 FIFO control register W 0x00 12.3.1.6/12-11 0x0_4502 UAFR—ULCR[DLAB] = 1 UART0 alternate function register R/W 0x00 12.3.1.12/12-17 0x0_4503 ULCR—ULCR[DLAB] = x UART0 line control register R/W 0x00 12.3.1.7/12-12 0x0_4504 UMCR—ULCR[DLAB] = x UART0 MODEM control register R/W 0x00 12.3.1.8/12-14 0x0_4505 ULSR—ULCR[DLAB] = x UART0 line status register R 0x60 12.3.1.9/12-15 0x0_4506 UMSR—ULCR[DLAB] = x UART0 MODEM status register R 0x00 12.3.1.10/12-16 0x0_4507 USCR—ULCR[DLAB] = x UART0 scratch register R/W 0x00 12.3.1.11/12-17 0x0_4510 UDSR—ULCR[DLAB] = x UART0 DMA status register R 0x01 12.3.1.13/12-18 0x0_4600 URBR—ULCR[DLAB] = 0 UART1 receiver buffer register R 0x00 12.3.1.1/12-6 0x0_4600 UTHR—ULCR[DLAB] = 0 UART1 transmitter holding register W 0x00 12.3.1.2/12-6 0x0_4600 UDLB—ULCR[DLAB] = 1 UART1 divisor least significant byte register R/W 0x00 12.3.1.3/12-7 0x0_4601 UIER—ULCR[DLAB] = 0 UART1 interrupt enable register R/W 0x00 12.3.1.4/12-9 0x0_4601 UDMB_ULCR[DLAB] = 1 UART1 divisor most significant byte register R/W 0x00 12.3.1.3/12-7 0x0_4602 UIIR—ULCR[DLAB] = 0 UART1 interrupt ID register R 0x01 12.3.1.5/12-10 0x0_4602 UFCR—ULCR[DLAB] = 0 UART1 FIFO control register W 0x00 12.3.1.6/12-11 0x0_4602 UAFR—ULCR[DLAB] = 1 UART1 alternate function register R/W 0x00 12.3.1.12/12-17 0x0_4603 ULCR—ULCR[DLAB] = x UART1 line control register R/W 0x00 12.3.1.7/12-12 0x0_4604 UMCR—ULCR[DLAB] = x UART1 MODEM control register R/W 0x00 12.3.1.8/12-14 0x0_4605 ULSR—ULCR[DLAB] = x UART1 line status register R 0x60 12.3.1.9/12-15 0x0_4606 UMSR—ULCR[DLAB] = x UART1 MODEM status register R 0x00 12.3.1.10/12-16 0x0_4607 USCR—ULCR[DLAB] = x UART1 scratch register R/W 0x00 12.3.1.11/12-17 0x0_4610 UDSR—ULCR[DLAB] = x UART1 DMA status register R 0x01 12.3.1.13/12-18 |
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