MPC8540 datasheet(482/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

12-4

Freescale Semiconductor

DUART

12.3 Memory Map/Register Definition

There are two complete sets of DUART registers (one for UART0 and one for UART1). The two

UARTs on the device are identical, except that the registers for UART0 are located at offsets

0x0_4500 (local), and the registers for UART1 are located at offsets 0x0_4600 (local). Throughout

this chapter, the registers are described by a singular acronym: for example, LCR represents the

line control register for either UART0 or UART1.

The 14 registers in each UART interface are used for configuration, control, and status. The divisor

latch access bit, ULCR[DLAB], is used to access the divisor latch least- and most-significant bit

registers and the alternate function register. Refer to Section 12.3.1.7, “Line Control Registers

(ULCR0, ULCR1),” for more information on ULCR[DLAB].

All the DUART registers are one byte wide. Reads and writes to these registers must be byte-wide

operations. Table 12-3 provides a register summary with references to the section and page that

Table 12-2. DUART Signals—Detailed Signal Descriptions

Signal

I/O

Description

UART_SIN[0:1]

Serial data in. Data is received on the receivers of UART0 and UART1 through its respective

serial data input signal, with the least-significant bit received first.

State

Meaning

Asserted/Negated—Represents the data being received on the UART interface.

Timing Assertion/Negation—An internal logic sample signal, rxcnt, uses the frequency of

the baud-rate generator to sample the data on SIN.

UART_SOUT[0:1]

O Serial data out. The serial data output signals for the UART0 and UART1 are set ('mark'

condition) when the transmitter is disabled, idle, or operating in the local loop-back mode. Data

is shifted out on these signals, with the least significant bit transmitted first.

State

Meaning

Asserted/Negated—Represents the data being transmitted on the respective UART

interface.

Timing Assertion/Negation— An internal logic sample signal, rxcnt, uses the frequency of

the baud-rate generator to update and drive the data on SOUT.

UART_CTS[0:1]

Clear to send. These active-low inputs are the clear-to-send inputs. They are connected to the

respective RTS outputs of the other UART devices on the bus. They can be programmed to

generate an interrupt on change-of-state of the signal.

State

Meaning

Asserted/Negated—Represent the clear to send condition for their respective UART.

Timing Assertion/Negation—Sampled at the rising edge of every CCB clock.

UART_RTS[0:1]

O Request to send. UART_RTSx are active-low output signals that can be programmed to be

automatically negated and asserted by either the receiver or transmitter. When connected to

the clear-to-send (CTS) input of a transmitter, this signal can be used to control serial data flow.

State

Meaning

Asserted/Negated—Represents the data being transmitted on the respective UART

interface.

Timing Assertion/Negation—Updated and driven at the rising edge of every CCB clock.

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