MPC8540 datasheet(486/1302 Pages) FREESCALE

486 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

12-8

Freescale Semiconductor

DUART

Figure 12-5 shows the bits in the UDLBs.

Table 12-7 describes the fields of UDLB registers.

Table 12-8 shows baud rate when the input clock is at certain frequencies.

To get the percent error value, the following three steps are taken:

1. The input clock frequency (ICF) is divided by the actual frequency input (AFI) to get the

correct divisor value (ICF/AFI where AFI = baud rate

× 16).

2. The divisor value is subtracted from 1.

UDLB

Reset

0x00

Offset

0x0_4500, 0x0_4600

Figure 12-5. Divisor Least Significant Byte Registers (UDLB0, UDLB1)

Table 12-7. UDLB Field Definition

Bits

Name

Description

0–7

UDLB

Divisor least-significant byte. This is concatenated with UDMB.

Table 12-8. Baud Rate Examples

Baud Rate

(Decimal)

Divisor

Input

Clock(CCB)

Frequency

(MHz)

Percent Error

(Decimal)

Decimal

Hex

9,600

1736

6C8

266

0.0064

19,200

868

364

266

0.0064

38,400

434

1B2

266

0.0064

56,000

298

12A

266

0.1280

128,000

130

266

0.1600

256,000

266

0.1600

9,600

2170

87A

333

0.0064

19,200

1085

43D

333

0.0064

38,400

543

21F

333

0.0858

56,000

372

174

333

0.0064

128,000

163

333

0.1472

256,000

333

0.4672

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